Abstract

Cloud computing promises flexibility, high performance, and low cost. Despite its prevalence, most datacenters hosting cloud computing services still operate at very low utilization, posing serious scalability concerns. There are several reasons behind low cloud utilization, dominated by overly conservative users trying to avoid the unpredictable performance of multi-tenancy.

A crucial system that can improve the efficiency of cloud infrastructures, while guaranteeing high performance for each submitted application is the cluster manager; the system that orchestrates where applications are placed and how many resources they receive. In this talk, I will first describe Quasar, a cluster management system that leverages practical ML techniques to quickly determine the type and amount of resources a new cloud application needs to satisfy its quality of service constraints. Quasar also introduces a new declarative interface in cluster management, where users express their applications’ performance, not resource, requirements to the system. We have built and deployed Quasar in local clusters, as well as production systems, including Twitter and AT&T, and showed that it guarantees high application performance, while improving system utilization by 2-3x.

Second, I will talk about the security vulnerabilities cloud multi-tenancy creates, and show how similar ML techniques to those used in Quasar can enable an adversary to extract confidential information about an application, and negatively impact its performance.

Finally, I will briefly discuss the direction in which cloud applications and systems are evolving, and how big data can help us improve the way we design and manage these complex, large-scale systems.

Abstract

The vast amount of new data being generated is outpacing the development of infrastructures and continues to grow at much higher rates than Moore’s law, a problem that is commonly referred to as the “data deluge problem”. This brings current computational machines in the struggle to exceed Exascale processing powers by 2020 and this is where the energy boundary is setting the second, bottom-side alarm: A reasonable power envelope for future Supercomputers has been projected to be 20MW, while world’s current No. 2 Supercomputer Sunway TaihuLight provides 93 Pflops and requires already 15.37 MW. This simply means that we have reached so far below 10% of the Exascale target but we consume already more than 75% of the targeted energy limit!

The way to escape is currently following the paradigm of disaggregating and disintegrating resources, massively introducing at the same time optical technologies for interconnect purposes. Disaggregating computing from memory and storage modules can allow for flexible and modular settings where hardware requirements can be tailored to meet the certain energy and performance metrics targeted per application. At the same time, optical interconnect and photonic integration technologies are rapidly replacing electrical interconnects continuously penetrating at deeper hierarchy levels: Silicon photonics have enabled the penetration of optical technology to the computing environment, starting from rack-to-rack and gradually shifting towards board-level communications. In this work, we will discuss the main performance and energy challenges currently faced by the computing industry and we will present our recent research on photonic technologies towards realizing resource disaggregation at all hierarchy levels spanning from rack- through board- down to disintegrated chip-scale computing. We will demonstrate high-port count optical switch layouts with up to 1024×1024 input/output ports that allow for low-latency values well below the 1μsec target of disaggregated DCs, while respective technology advances on electro-optical PCBs and Silicon Photonic transceiver and routing elements towards realizing on-board resource disaggregation for multi-socket compute node applications will be overviewed. Finally, the transfer of resource disaggregation to chip-scale environment and the deployment of disintegrated computational setups will be discussed, highlighting how novel photonic Network-on-Chip technologies and emerging optical RAM and optical cache memory technologies can shape a radically new chip-level computing environment with increased granularity, modularity, performance and energy efficiency.

This work has been carried out within the frame of the European FP7 projects RAMPLAS and PhoxTrot and the H2020 projects ICT-STREAMS, L3MATRIX and dREDBox.

Abstract

FPGA and GPU based accelerators have recently become first class citizens in datacenters. Despite their high cost, however, accelerators remain underutilized for large periods of time, as vendors prefer to dedicate them to workloads for guaranteed QoS. At the same time, accelerator sharing is difficult, due to vendor locked communication paths with software applications. In this work in progress, we modified the agents of Apache Mesos with Vinetalk, an accelerator middleware that abstracts the entire communication path between OS processes and accelerator hardware without adding more than 10% performance overhead. We demonstrate the ease of integration of software applications with GPUs and, in collaboration with ICCS with FPGA logic. Finally, we show that the use of Vinetalk-enhanced Mesos allows analytics pipelines, such as Apache Spark, to use for the first time executors with heterogeneous characteristics.

Abstract

In this work we introduce RCU-HTM, a technique that combines Read-Copy-Update (RCU) with Hardware Transactional Memory (HTM) to implement highly efficient concurrent Binary Search Trees (BSTs). Similarly to RCU-based algorithms, we perform the modifications of the tree structure in private copies of the affected parts of the tree rather than in-place. This allows threads that traverse the tree to proceed without any synchronization and without being affected by concurrent modifications. The novelty of RCU-HTM lies at leveraging HTM to permit multiple updating threads to execute concurrently. After appropriately modifying the private copy, we execute an HTM transaction, which atomically validates that all the affected parts of the tree have remained unchanged since they’ve been read and, only if this validation is successful, installs the copy in the tree structure.

We apply RCU-HTM on AVL and Red-Black balanced BSTs and compare their performance to state-of-the-art lock-based, non-blocking, RCU- and HTM-based BSTs. Our experimental evaluation reveals that BSTs implemented with RCU-HTM achieve high performance, not only for read-only operations, but also for update operations. More specifically, our evaluation includes a diverse range of tree sizes and operation workloads and reveals that BSTs based on RCU-HTM outperform other alternatives by more than 18%, on average, on a multi-core server with 44 hardware threads.

Abstract

Review-based recommender systems have become dominant in recent years. In these systems, the traditional user-item ratings’ matrix is augmented with textual evaluations of the items by the users. In this talk, we are going to explore how this extra information source can be incorporated in matrix factorization algorithms, which constitute the state-of-the-art in recommender systems. More specifically, we will examine a special category of machine learning techniques for text analysis known as neural language models. The talk will conclude with the presentation of some preliminary results of the discussed techniques on reference datasets.

Abstract

Task-based dataflow programming models and runtimes are promising candidates for programming multicore and manycore architectures. These programming models analyze dynamically task dependencies at runtime and schedule independent tasks concurrently to the processing elements. In such models, cache locality and efficient utilization of the on-chip cache resources is critical for performance and energy efficiency. In this talk we will describe a number of combined hardware-software approaches to improve data movement and locality in the cache hierarchy and better utilize the on-chip cache resources. We will also present our recent research activities on interconnects and communication primitives for exascale systems.

Abstract

The advent of the Big Data era has given birth to a variety of new architectures aiming at applications with increased scalability, robustness and fault tolerance. At the same time, though, these architectures have complicated the application structure, leading to an exponential growth of the applications’ configuration space and increased difficulty in predicting their performance.

In this work, we describe a novel, automated profiling methodology that makes no assumptions on application structure. Our approach utilizes oblique Decision Trees in order to recursively partition an application’s configuration space in disjoint regions, choose a set of representative samples from each subregion according to
a defined policy and return a model for the entire space as a composition of linear models over each subregion.

An extensive evaluation over real-life applications and synthetic performance functions showcases that our scheme outperforms other state-of-the-art profiling methodologies. It particularly excels at reflecting abnormalities and discontinuities of the performance function, allowing the user to influence the sampling policy based on the modeling accuracy and the space coverage.